Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

CROSS REFERENCES TO RELATED APPLICATIONS

This application is a Reissue application of application Ser. No.14/244,910, filed Mar. 25, 2014, now U.S. Pat. No. 9,024,662, issued onMay 5, 2015, which is a Continuation of application Ser. No. 13/551,353,filed on Jul. 17, 2012, now U.S. Pat. No. 8,742,793, issued on Jun. 3,2014, which is a Continuation of application Ser. No. 13/064,731, filedApr. 12, 2011, now U.S. Pat. No. 8,299,818, issued on Oct. 30, 2012,which is a Continuation of application Ser. No. 12/656,219, filed Jan.21, 2010, now U.S. Pat. No. 7,944,243, issued on May 17, 2011, which isa Continuation of application Ser. No. 12/285,375, filed Oct. 2, 2008,now U.S. Pat. No. 7,750,681, issued on Jul. 6, 2010, which claimspriority from Japanese Application Number 2007-289250, filed on Nov. 7,2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuithaving a power supply switch cell that controls supplying of supplyvoltage or reference voltage to a circuit cell and blocking of thevoltage supplying.

2. Description of Related Art

To control supplying of supply voltage or reference voltage to a circuitcell and blocking of the voltage supplying is known as, for example, acircuit technique called multi-threshold complementary metal oxidesemiconductor (MTCMOS). In the MTCMOS, for example, for each circuitblock having a specific function, a power supply switch transistor withthreshold voltage higher than that of a transistor in a functionalcircuit is connected to the path of the supplying of the supply voltageor the reference voltage (e.g. GND voltage). When the circuit blockenters the unused state, the power supply switch transistor is set tothe off-state, so that the leakage current that flows through therespective transistors in the circuit block is blocked. This cansignificantly reduce the leakage current that flows through the circuitblock in the unused state.

For the purpose of eliminating a troublesome task of arranging powersupply switch transistors based on manpower in design of a semiconductorintegrated circuit including a circuit block to which the MTCMOStechnique is applied, the inventors of the present application havealready proposed a semiconductor integrated circuit in which powersupply switch transistors are included as cells and the power supplyswitch cells are properly disposed in the area in which circuit cellsare arranged (refer to Japanese Patent Laid-open No. 2005-259879(hereinafter referred to as Patent Document1)).

SUMMARY OF THE INVENTION

There is a need for the present invention to add improvement to thesemiconductor integrated circuit with the structure in which the powersupply switch cells are disposed as proposed in Patent Document 1 sothat power supply noise can be further suppressed.

According to an embodiment of the present invention, there is provided asemiconductor integrated circuit including a main-interconnect to whichsupply voltage or reference voltage is applied, a plurality ofsub-interconnects, a plurality of circuit cells configured to beconnected to the plurality of sub-interconnects, and a power supplyswitch cell configured to control, in accordance with an input controlsignal, connection and disconnection between the main-interconnect andthe sub-interconnect to which a predetermined one of the circuit cellsis connected, of the plurality of sub-interconnects. The semiconductorintegrated circuit further includes an auxiliary interconnect configuredto connect the plurality of sub-interconnects to each other.

In the embodiment of the present invention, it is preferable that aplurality of the power supply switch cells be disposed on a line along adirection in parallel to or perpendicular to the direction along whichthe main-interconnect is disposed and be connected to a plurality ofcontrol lines in accordance with a predetermined connection rule.

In the above-described configuration, before the power supply switchcell is turned on, equalization of the amount of accumulated chargesamong the plurality of sub-interconnects connected to the plurality ofcircuit cells is carried out via the auxiliary interconnect. Thus,compared with the case of providing no auxiliary interconnect, the peakof power supply noise arising in the main-interconnect when the powersupply switch is turned on first is sufficiently suppressed.

The embodiment of the present invention offers an advantage that powersupply noise can be suppressed effectively and sufficiently in asemiconductor integrated circuit in which power supply switchtransistors are included as cells and the power supply switch cells areproperly disposed in the area in which circuit cells are arranged.Furthermore, the embodiment of the present invention offers advantagesof reduction in leakage, reduction in the area of the power supplyswitch cell, and shortening of the design period in defining of theswitch cells that should be turned on.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing one example of the configuration of asemiconductor integrated circuit relating to an embodiment of thepresent invention;

FIG. 2 is a diagram showing one example of the layout of thesemiconductor integrated circuit relating to the embodiment;

FIG. 3A is a diagram schematically showing the configuration of an areaA1 in the semiconductor integrated circuit relating to the embodiment,and FIGS. 3B1 and 3B2 are diagrams showing the structure of lines alongthe row direction (interconnect form);

FIG. 4 is a diagram showing the inter-cell connection relationship ofthe interconnects of FIG. 3B1 based on a 4×2 cell arrangement;

FIG. 5 is a diagram showing the inter-cell connection relationship ofthe interconnects of FIG. 3B2 based on a 4×2 cell arrangement;

FIG. 6 is a diagram showing a specific form of the connection betweeninterconnects and power supply switch cells in the semiconductorintegrated circuit relating to the embodiment;

FIG. 7 is a diagram showing another specific interconnect form of thesemiconductor integrated circuit relating to the embodiment; and

FIG. 8 is a diagram that arises from partial modification of FIG. 6 andis used for explaining advantages of the semiconductor integratedcircuit relating to the embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described below withreference to the accompanying drawings.

<Entire Configuration>

FIG. 1 is a diagram showing one example of the configuration of asemiconductor integrated circuit relating to the embodiment of thepresent invention. In FIG. 1, interconnects for supplying supply voltageand reference voltage (e.g. GND voltage) and circuit cells connected tothe interconnects are schematically illustrated.

The semiconductor integrated circuit shown in FIG. 1 has plural pairs ofpower supply lines PL1 as the “main-interconnect”, plural pairs of powersupply lines PL2, plural branch line groups BL1, plural branch linegroups BL2 as the “sub-interconnect”, plural circuit cells 10, pluralpower supply switch cells 20, a circuit block 30, and plural powersupply input cells 41 and 42.

The pairs of power supply lines PL1 extend along the column direction,and are disposed in parallel to each other with the intermediary of apredetermined distance therebetween along the row direction.

The pairs of power supply lines PL2 extend along the row directionperpendicular to the pairs of power supply lines PL1, and are disposedin parallel to each other with the intermediary of a predetermineddistance therebetween along the column direction.

In FIG. 1, five pairs of power supply lines PL1 and five pairs of powersupply lines PL2 intersect with each other, and form a power supply linepattern in a lattice manner as a whole.

In each of the pairs of power supply lines PL1 and PL2, one supplyvoltage main line VDD and one reference voltage main line VSS aredisposed in parallel to each other so as to form one pair. At theintersections in this lattice power supply line pattern, the supplyvoltage main lines VDD are connected to each other via a contact and thereference voltage main lines VSS are connected to each other via acontact.

In the lattice power supply line pattern, the power supply input cells41 and 42 are connected to each of the pairs of power supply lines PL1and PL2 on four outer frames of the power supply line pattern. Thereference voltage main line VSS is connected to the power supply inputcell 41, and the supply voltage main line VDD is connected to the powersupply input cell 42.

Reference voltage Vss is supplied from the external of the semiconductorintegrated circuit via the power supply input cell 41. Supply voltageVdd is supplied from the external of the semiconductor integratedcircuit via the power supply input cell 42.

The branch line groups BL1 and BL2 arise from branching from the pair ofpower supply lines PL1 as the “main-interconnect”, and provide power tothe circuit cells 10 as the basic unit of the circuit in thesemiconductor integrated circuit.

Each of the branch line groups BL1 and BL2 is so formed as to extendalong the row direction from the pair of power supply lines PL1 as the“main-interconnect” extending along the column direction.

A plurality of such branch line groups arise from one pair of powersupply lines PL1, and the plural circuit cells 10 are connected to eachbranch line group.

The circuit cell 10 included in the semiconductor integrated circuitreceives power supplying from two branch lines connected to this circuitcell 10, i.e., from the branch line to which the supply voltage Vdd isapplied and the branch line to which the reference voltage Vss isapplied.

On the other hand, a circuit for which blocking of the power supply lineis unnecessary, such as a continuous operating circuit, receives powersupplying not via a branch line group but directly from a pair of powersupply lines, like, for example, the circuit block 30 shown in FIG. 1.

The branch line group BL1 includes a supply voltage branch line VDDA anda reference voltage branch line VSSA as the above-described two branchlines for power supplying to the circuit cells 10. The supply voltagebranch line VDDA is connected to the supply voltage main line VDD, andthe reference voltage branch line VSSA is connected to the referencevoltage main line VSS.

The branch line group BL2 includes a supply voltage branch line VDDB anda reference voltage branch line VSSB as the above-described two branchlines. The supply voltage branch line VDDB is connected to the supplyvoltage main line VDD, and the reference voltage branch line VSSB isconnected to the reference voltage main line VSS.

The difference between the branch line groups BL1 and BL2 is thepresence and absence of provision of the power supply switch cell 20.Specifically, the power supply switch cell 20 is provided between thebranch line group BL2 and the pair of power supply lines PL1, while thepower supply switch cell 20 is not provided between the branch linegroup BL1 and the pair of power supply lines PL1. Of the branch linegroups BL1 and BL2, the branch line group BL2 is equivalent to oneexample of the “sub-interconnect” because the connection of the branchline group BL2 to the pair of power supply lines PL1 is controlled bythe power supply switch cell 20.

A control signal (not shown) is input to the power supply switch cell20. In response to this signal input, the power supply switch cell 20can block at least one of the supply voltage and the reference voltagebetween the pair of power supply lines PL1 and the branch line groupBL2. For example, the power supply switch cell 20 includes a powersupply switch transistor, and turns off the power supply switchtransistor in accordance with the logic level of the input controlsignal to thereby block the power supply current path to the circuitcell 10 connected to the branch line group BL2.

In the case of a semiconductor integrated circuit of the MTCMOS type, aMOS transistor with threshold voltage higher than that of a transistorof the same conductivity type in the circuit cell 10 is used as thepower supply switch transistor. For example, in the case of electricallydisconnecting the reference voltage branch line VSSB from the referencevoltage main line VSS in accordance with the control signal, an n-typeMOS transistor having high threshold voltage is used as the power supplyswitch transistor. In the case of electrically disconnecting the supplyvoltage branch line VDDB from the supply voltage main line VDD inaccordance with the control signal, a p-type MOS transistor having highthreshold voltage is used as the power supply switch transistor.

FIG. 2 is a diagram showing one example of the layout of thesemiconductor integrated circuit relating to the present embodiment.

In FIG. 2, numeral “40” indicates input/output cells (hereinafter,referred to as the IO cells) including the power supply input cells 41and 42. The same symbol or numeral in FIGS. 1 and 2 indicates the samecomponent.

For a rectangular semiconductor chip in which the semiconductorintegrated circuit is formed, plural IO cells 40 arranged on a line aredisposed on the peripheral part of the semiconductor chip along foursides thereof. In the area surrounded by these IO cells 40, theabove-described lattice power supply line pattern is formed.

Referring to FIG. 1, the area inside the outer frame part of the powersupply line pattern in FIG. 2 is roughly categorized into an area A1 towhich the MTCMOS technique is applied, an area A2 to which the MTCMOStechnique is not applied, and the other area to which the MTCMOStechnique is not applied. Specifically, the area A1 corresponds to thearea in which the circuit cell 10 connected to the branch line group BL2as the “sub-interconnect” is disposed and for which power supplying canbe blocked by the power supply switch cell 20. The area A2 correspondsto the area in which the circuit cell 10 connected to the branch linegroup BL1 is disposed. The other area corresponds to the area in which acircuit operates through reception of power supplying directly from thepair of power supply lines PL2 (PL1 is also possible) (in FIG. 1, theother area corresponds to the area in which the circuit block 30 isdisposed).

The ranges of the areas A1 and A2 shown in FIG. 2 can be flexiblydefined through selection as to whether or not to provide the powersupply switch cell 20 between the pair of power supply lines PL1 and thebranch line group.

<Connection Structure of Control Lines>

In FIGS. 1 and 2, illustration of control lines for controlling thepower supply switch cells 20 is omitted. Connection of the control linesto the power supply switch cells 20, suitable for the presentembodiment, will be described below.

As shown in FIG. 1, the power supply switch cells 20 are disposed inparallel to the pair of power supply lines PL1 as the“main-interconnect”. In the example of FIG. 1, the power supply switchcells 20 are arranged on one line along the column direction.

FIG. 3A is a diagram showing the arrangement in the area A1. FIG. 3Aschematically shows the structure of connection of control lines to arow of the power supply switch cells 20.

As shown in FIG. 3A, the power supply switch cells 20 are arranged alongthe column direction, and are connected to a first control line CL1 at aratio of one out of four power supply switch cells 20. Furthermore,three consecutive other power supply switch cells 20 between the powersupply switch cells 20 connected to the first control line CL1 areconnected to a second control line CL2.

A buffer circuit BUF is provided in a proper intermediate position ofeach of the first control line CL1 and the second control line CL2. Theprovision of the buffer circuit BUF is to rectify a control signalattenuated in the middle of its transmission into a waveform having theamplitude between the supply voltage Vdd and the reference voltage Vss.The buffer circuit BUF is disposed at least in the IO cells 40 of FIG.2. In addition, the buffer circuit BUF may be properly disposed in thearea surrounded by the IO cells 40 of FIG. 2 as necessary.

Although the above-described example is a connection example of twocontrol lines, three or more control lines may be provided.

In any case, the control lines are connected to the control nodes (thegates of the power supply switch transistors) of the respective powersupply switch cells 20 arranged on a line, in accordance with apredetermined connection rule. Although the predetermined connectionrule in the above-described example is that “the power supply switchcells 20 are connected at a ratio of one to three”, any rule may beoptionally employed.

The reason why the plural power supply switch cells 20 are controlled bythe plural control lines is as follows.

In the MTCMOS technique, as the way of the provision of the power supplyswitch transistor (the power supply switch cell 20), the following threeways are available: it is provided between the supply voltage branchline VDDB and the supply voltage main line VDD connected to the circuitcell 10 whose activation and stop are repeated; it is provided betweenthe reference voltage branch line VSSB and the supply voltage main lineVDD connected to this circuit cell 10; and it is provided at both ofthese positions. In the present embodiment, the former two ways can beemployed. Moreover, because the drive capability of an n-type MOStransistor is higher than that of a p-type MOS transistor, it isdesirable that the power supply switch cell 20 be provided between thereference voltage branch line VSSB and the supply voltage main line VDDconnected to the circuit cell 10. In the following, the description willbe continued on the premise of this desirable case.

In the area A1 (see FIGS. 1 and 2), to which the MTCMOS technique isapplied, if the period of the off-state of the power supplying to thecircuit cell 10 is long, the reference voltage branch line VSSB is oftencharged to high potential due to the transistor leakage current in thecircuit cell 10. In this case, if all of the power supply switch cells20 in the activation-target area are switched from the off-state to theon-state by one control line, large discharge current will flow throughthe supply voltage main line VDD, and this will result in power supplynoise to the other area and the other circuit blocks.

In contrast, if plural control lines are provided as shown in FIG. 3Aand control is so carried out that the number of power supply switchcells 20 in the on-state is gradually increased by the plural controllines based on the predetermined connection rule, the peak value of thispower supply noise can be suppressed.

The position at which the row of the power supply switch cells 20 isprovided may be overlapped with the pair of power supply lines PL1 asshown in FIG. 1. Specifically, the power supply switch transistor of thepower supply switch cell 20 is formed in a substrate region below thesupply voltage main line VDD as the “main-interconnect” of the pair ofpower supply lines PL1. By utilizing an interconnect at another layerlevel, different from the supply voltage main line VDD, of themultilayer interconnect structure, the reference voltage branch lineVSSB as the “sub-interconnect” is formed. Furthermore, the connectionbetween the power supply switch transistor and the reference voltagebranch line VSSB and the connection between the power supply switchtransistor and the reference voltage main line VSS are realized by usingcontacts.

Various forms are available regarding the multilevel use form,connection, and interconnect pattern of the multilayer interconnect inthe overlapping part between the power supply switch cells 20 and thepair of power supply lines PL1. Regarding these points, various formsdescribed in the previous application (Japanese Patent Laid-open No.2005-259879) by the inventors of the present application can beemployed.

In FIG. 3A, each branch line along the row direction is represented asone line. However, in practice, for example, the form of FIG. 3B1 orFIG. 3B2, which shows part A in an enlarged manner, can be employed.

FIG. 3B1 shows the case in which each of the supply voltage branch lineVDDB and the reference voltage branch line VSSB is shared by two circuitcells 10 adjacent to each other along the column direction like threecircuit cells given numeral “10” in FIG. 3A. In this case, each linealong the row direction in FIG. 3A indicates one interconnect, and thesupply voltage branch line VDDB and the reference voltage branch lineVSSB are alternately disposed along the column direction as a whole.

FIG. 4 shows the inter-cell connection relationship of the interconnectsof FIG. 3B1 based on a 4×2 cell arrangement.

In FIG. 4, the supply voltage branch line VDDB and the reference voltagebranch line VSSB are alternately disposed along the column direction,and each of the supply voltage branch line VDDB and the referencevoltage branch line VSSB is shared by two cells adjacent to each otheralong the column direction. Thus, one cell, for example, a circuit cell10A (10B), has an interconnect segment having the width half of thewidth of the supply voltage branch line VDDB and another interconnectsegment having the width half of the width of the reference voltagebranch line VSSB. Therefore, this interconnect structure will bereferred to as the “two-line system.”

If the circuit cell group shown in FIG. 4 includes circuit cells forwhich power supplying is always necessary (in FIG. 1, the circuit cellsdisposed in the area A2), the reference voltage branch line VSSB isdirectly connected to the main-interconnect (kept at the referencevoltage Vss) along the column direction. On the other hand, if thecircuit cell group shown in FIG. 4 includes circuit cells for whichpower supplying needs to be blocked (in FIG. 1, the circuit cellsdisposed in the area A1 separately from the area A2), the referencevoltage branch line VSSB is connected to the main-interconnect (kept atthe reference voltage Vss) via the power supply switch cell 20.

On the assumption that the circuit to be formed is the same and theinput/output node is positioned at the center of the cell height (alongthe column direction, i.e. the vertical direction of FIG. 4), a circuitcell 10B can be disposed through copying of the circuit cell 10A andinversion (flip) thereof about the center line of the reference voltagebranch line VSSB.

FIG. 3B2 shows the interconnect structure called the “three-line system”in the above-mentioned previous application (Japanese Patent Laid-openNo. 2005-259879). In the three-line system, for example, three referencevoltage branch lines VSSB are disposed in proximity to each other, whileone supply voltage branch line VDDB is disposed in an isolated manner.

FIG. 5 shows the inter-cell connection relationship of the interconnectsof FIG. 3B2 based on a 4×2 cell arrangement.

A reference voltage branch line VSSB(0) as the center line of threeadjacent branch lines is shared by two cells adjacent to each other, andthe supply voltage branch line VDDB is also shared by two cells adjacentto each other. Thus, for one cell, for example, a circuit cell 10A(10B), the three-line system based on the following three lines isformed: an interconnect segment having the width half of the width ofthe reference voltage branch line VSSB(0), an interconnect segmenthaving the width half of the width of the supply voltage branch lineVDDB, and another reference voltage branch line VSSB(A) (or VSSB(B))between these interconnect segments.

The purpose of forming the branch line group based on three adjacentreference voltage branch lines VSSB is to allow the circuit cell forwhich power supply is always necessary (in FIG. 1, the circuit celldisposed in the area A2 separately) to be freely disposed in a branchline group in the area A1.

In the circuit cell 10A shown in FIG. 5, for example, a circuit cellthat always receives power supplying and thus should be disposed in thearea A2 of FIG. 1 is connected between the reference voltage branch lineVSSB(0) as the center line of three adjacent branch lines and the supplyvoltage branch line VDDB. The power supply switch cell 20 is connectedbetween the center reference voltage branch line VSSB(0) and anotherreference voltage branch line VSSB(A) (or VSSB(B)), and a circuit cellin the area A1 for which power supplying is controlled by the powersupply switch cell 20 is connected between this reference voltage branchline VSSB(A) (or VSSB(B)) and the supply voltage branch line VDDB.

On the assumption that the circuit to be formed is the same and theinput/output node is positioned at the center of the cell height (alongthe column direction, i.e. the vertical direction of FIG. 5), a circuitcell 10B can be disposed through copying of the circuit cell 10A andinversion (flip) thereof about the center line of the reference voltagebranch line VSSB.

Even when the reference voltage branch lines VSSB look as one line ortwo lines as the planar pattern, the interconnect structure isencompassed in the category of the “three-line system” if the referencevoltage branch lines VSSB having the function as three lines asdescribed above are formed in the multilayer interconnect structure.

Either the “two-line system” of FIG. 3B1 or the “three-line system” ofFIG. 3B2 may be employed optionally. Furthermore, interconnectstructures of the different systems may be mounted on different areas ofthe same semiconductor integrated circuit in a mixed manner.

As specific forms regarding the multilevel use form, connection, andinterconnect pattern of the multilayer interconnect in the “two-linesystem” and the “three-line system”, various forms described in theprevious application (Japanese Patent Laid-open No. 2005-259879) by theinventors of the present application can be employed.

The following advantages are achieved by the above-described structurein which the interconnect for supplying the supply voltage Vdd or thereference voltage Vss is composed of the main-interconnect (the supplyvoltage main line VDD or the reference voltage main line VSS) and thesub-interconnect (the supply voltage branch line VDDB or the referencevoltage branch line VSSB) and the power supply switch cell 20 isprovided between the necessary main-interconnect and sub-interconnect.

Specifically, it is possible to widely disperse the power supply switchcells 20 in the area in which the circuit cell 10 can be disposed andfinely carry out blocking of power supplying by the power supply switchcell 20 for each circuit cell group including a comparatively-smallnumber of circuit cells.

Thus, compared with a method of providing a power supply switch for eachcircuit block, the supply current that flows through the power supplyswitch cell 20 is reduced, and thus a supply voltage drop is decreased.This can alleviate the influence of the voltage drop arising in thepower supply switch cell 20 on signal delay.

Furthermore, compared with a method of disposing a power supply switchoutside a circuit block, the flexibility of the arrangement of the powersupply switch cell 20 is enhanced, and thus the area A1, for whichblocking of power supplying is carried out, can be flexibly defined.This makes it possible to easily realize automatic design of the layoutincluding the power supply switch cell 20. In particular, in the“three-line system”, the area A1, for which blocking of power supplyingis carried out, and the area A2, for which blocking of power supplyingis not carried out, can be formed in one area in a mixed manner withoutbeing separated from each other.

This can reduce the burden of the design task, which is tackled based onmanpower in a related art, and thus can shorten the development time.

If, of the plural power supply switch cells 20, different cell groupseach including a predetermined number of power supply switch cells 20are separately controlled by plural different control lines, theabove-described advantage that the peak value of power supply noise canbe suppressed is achieved.

In the present embodiment, in addition to the above-describedconfiguration, an auxiliary interconnect 50 is provided as shown in FIG.3A for the purpose of achieving a larger effect to suppress the powersupply noise. The auxiliary interconnect 50 intersects with the supplyvoltage branch line VDDB and the reference voltage branch line VSSBdisposed along the row direction, and thus is formed of an interconnectlayer at a layer level different from that of these branch lines. Theauxiliary interconnect 50 connects the reference voltage branch linesVSSB shown in FIGS. 3B1 and 3B2 to each other. However, the auxiliaryinterconnect 50 may not be connected to a line to which a circuit cellof the area A2, for which blocking of power supplying is not carriedout, is connected, such as the center reference voltage branch line VSSBin the interconnect structure including three branch lines disposedadjacent to each other, shown in FIG. 3B2, if there is a need toeliminate the influence of giving signal delay to this circuit cell.

In FIG. 3A, both the configuration in which the power supply switchcells 20 are controlled by plural control lines and the provision of theauxiliary interconnect 50 are employed. However, in the presentembodiment, it is sufficient that at least the auxiliary interconnect 50is provided.

If the auxiliary interconnect 50 is not provided, when the potential ofa certain reference voltage branch line VSSB is the highest, chargesaccumulated in the reference voltage branch line VSSB with thispotential are discharged to the reference voltage main line VSS at aburst, and thus the peak of power supply noise arising in the referencevoltage main line VSS becomes high.

In contrast, if the auxiliary interconnect 50 is provided, the amount ofaccumulated charges is equalized among the plural reference voltagebranch lines VSSB before this discharging. Thus, providing the auxiliaryinterconnect 50 connecting the plural reference voltage branch linesVSSB to each other offers an effect to suppress the peak of power supplynoise.

The suppression of the peak value of power supply noise can be achievednot only by providing the auxiliary interconnect 50 to thereby equalizethe amount of accumulated charges before discharging but also byincreasing the connection impedance at the time of power supplyswitching. That is, this is equivalent to a method of decreasing thesize of the outlet of discharged charges.

In the case of controlling the power supply switch cells 20 by pluralcontrol lines, the connection impedance at the time of the first powersupply switching, which determines the peak value of power supply noise,can be increased compared with the case of simultaneously turning on allof the power supply switch cells 20. Thus, the effect to suppress thepower supply noise is achieved.

Employing both the auxiliary interconnect 50 and power supply switchingby plural control lines offers the following advantages. Specifically,due to the power supply switching by plural control lines, the amount ofcharges discharged per unit time from the reference voltage branch lineVSSB to the reference voltage main line VSS (the amount of charges thatlead to power supply noise) decreases as described above, and thus theeffect to suppress the peak of power supply noise is achieved asdescribed above. In addition, due to the equalization of accumulatedcharges via the auxiliary interconnect 50 before power supply switching,the peak of the power supply noise can be further suppressed.

Consequently, if the auxiliary interconnect 50 is provided, power supplynoise can be effectively suppressed attributed to both the provision ofthe auxiliary interconnect 50 and the power supply switching by pluralcontrol lines.

The above-described rule that determines the control of the power supplyswitch cells 20, such as the ratio of the number of power supply switchcells 20 that are switched on first to the number of power supply switchcells 20 that are switched on subsequently, is determined inconsideration of the interconnect resistance, interconnect capacitance,and so on of the auxiliary interconnect 50.

Inversely, in matching with the number of switch transistors that arecontrolled at one time, the interconnect resistance of the auxiliaryinterconnect 50 and the layer level used for the auxiliary interconnect50 may be so determined that the peak of power supply noise can besufficiently suppressed. However, because the limit regarding theprocess is imposed on the interconnect resistance of the auxiliaryinterconnect 50 and the layer level used therefor, the former method, inwhich the number of power supply switch cells 20 that are switched on atone time is adjusted in matching with the specification of the auxiliaryinterconnect 50, is easier.

If the power supply switch cells 20 that are connected to the firstcontrol line CL1 and are switched on first are uniformly arranged withthe intermediary of an equal distance therebetween as shown in FIG. 3A,the effect to suppress power supply noise is further enhanced becausesuch an arrangement manner is suitable for the equalization of theamount of charges by the auxiliary interconnect 50.

Furthermore, if the auxiliary interconnect 50 is provided, the followingadvantages are achieved due to the equalization of the current thatstarts to flow from the reference voltage branch line VSSB to thereference voltage main line VSS when the circuit cell 10 is returnedfrom the state in which power supplying thereto is blocked: thetransistor size can be decreased; the design is facilitated and thus thedesign period can be shortened; and leakage current can be reduced.Details of these advantages will be described below.

SPECIFIC EXAMPLES

FIG. 6 is a diagram showing a more specific interconnect example.

In the present example, the above-described reference voltage main lineVSS (FIG. 1) along the column direction is composed of a first referencevoltage main line VSS1 along the row direction and a second referencevoltage main line VSS2 along the column direction, formed of aninterconnect layer above that of the first reference voltage main lineVSS1. Of these main lines, the first reference voltage main line VSS1 isequivalent to the “main-interconnect”.

On both the sides of the first reference voltage main line VSS1 alongthe width direction thereof, two reference voltage branch lines VSSB aredisposed. The reference voltage branch lines VSSB are connected to eachother via contacts CN1 and the auxiliary interconnect 50. These firstreference voltage main line VSS1 and two reference voltage branch linesVSSB may be formed of an interconnect layer of the same layer level,such as a metal interconnect layer as the second layer.

The first reference voltage main line VSS1 is connected to the secondreference voltage main line VSS2 of the upper layer via contacts CN2. Ina substrate region below the interconnect layer level of the firstreference voltage main line VSS1, power supply switch transistors SW1and SW2 are formed. The power supply switch transistor SW1 is connectedbetween one reference voltage branch line VSSB and the first referencevoltage main line VSS1, and the power supply switch transistor SW2 isconnected between the other reference voltage branch line VSSB and thefirst reference voltage main line VSS1.

The above-described configuration is repeated along the columndirection.

In the configuration shown in FIG. 6, when one of the power supplyswitch transistors SW1 and SW2 is turned on, charges in the referencevoltage branch line VSSB connected to the turned-on transistor, of tworeference voltage branch lines VSSB disposed on both the sides of thefirst reference voltage main line VSS1, are discharged via the turned-ontransistor. At this time, because the reference voltage branch linesVSSB are connected to each other by the auxiliary interconnect 50,charges accumulated in the other reference voltage branch line VSSB movein linkage with the decrease in the potential of the reference voltagebranch line VSSB from which the charges are discharged via the turned-ontransistor. This can decrease the charges accumulated in the otherreference voltage branch line VSSB, too. However, the peak value ofpower supply noise is determined by the amount of charges accumulated inthe reference voltage branch line VSSB connected to the power supplyswitch transistor SW1 at the initial stage of the turning-on of thepower supply switch transistor SW1, and does not depend on the amount ofcharges that move slowly due to the auxiliary interconnect 50 after theturning-on of the transistor SW1. Therefore, due to the equalization ofthe amount of charges that should be discharged before power supplyswitching, the charge discharging that determines the peak value ofpower supply noise is slow, which suppresses the power supply noisearising in the second reference voltage main line VSS2.

Another specific example is shown in FIG. 7.

In this example, the reference voltage branch line VSSB and the supplyvoltage main line VDD are alternately disposed. This arrangementcorresponds to the “two-line system” similar to that of FIG. 3B1.However, in FIG. 7, the supply voltage main line VDD is disposed alongthe row direction and has no branch line, unlike the structure of FIG.3B1.

Furthermore, the power supply switch cell 20 including the power supplyswitch transistor SW1 of FIG. 6 and the power supply switch cell 20including the second switch SW2 are so disposed as to share thereference voltage branch line VSSB. Adjacent to the power supply switchtransistor SW1, a power supply switch transistor SW0 that shares thesupply voltage main line VDD with the power supply switch transistor SW1is disposed. Adjacent to the power supply switch transistor SW2, a powersupply switch transistor SW3 that shares the supply voltage main lineVDD with the power supply switch transistor SW2 is disposed.

In order to achieve the effect to suppress power supply noise similar tothe above-described effect, the reference voltage branch lines VSSB areconnected to each other by the auxiliary interconnect 50.

FIG. 8 shows a configuration obtained by adding the circuit cells 10arranged at random to the configuration of FIG. 6. With reference toFIG. 8, a description will be made below about an effect to decreasevariation in the power consumption at the time of the operation of thecircuit cells, attributed to the provision of the auxiliary interconnect50, and other effects. In FIG. 8, illustration of the second referencevoltage main line VSS2 is omitted.

The circuit cells 10 are arranged at random as shown in FIG. 8, forexample. The operation patterns of the respective circuit cells 10 arealso not uniform but determined based on operation assumed at the timeof the design. Therefore, the VSS potentials of the respective circuitcells 10 greatly vary depending on the places of the circuit cells andthe time. Thus, the plural circuit cells 10 involve variation in thepower consumption at the time of the operation thereof although theyhave the same circuit configuration. Consequently, if it is assumed thatthe auxiliary interconnect 50 is not provided, the currents that flowthrough four reference voltage branch lines VSSB in FIG. 8 also vary. Inthe case of selecting the switches that should be switched on based onprediction of this variation, the currents that flow through therespective reference voltage branch lines VSSB need to be predicted fromthe power consumption values of the respective circuit cells 10, whichdynamically change. Therefore, it is expected that the design involves alot of trouble and the design period increases. In addition, in order toassure the desired operation, the switches SW0 to SW3 need to bedesigned to have a size larger than the necessary size, with some degreeof margin. Such a switch with a large size has low on-resistance andhigh capability of charge discharging, and thus enhances the safeness toassure the operation. However, such a switch involves disadvantages ofcausing increase in the circuit area and increase in leakage current.

In the present embodiment, these disadvantages are eliminated becausethe auxiliary interconnect 50 is provided. Specifically, the movement ofcharges via the auxiliary interconnect 50 eliminates variation in thecurrent among the reference voltage branch lines VSSB. Therefore, nomatter which of the switches SW0 to SW3 is switched on, the equalizedcurrent will flow through the selected and turned-on switch.

Consequently, the provision of the auxiliary interconnect 50 facilitatesthe selection of the power supply switch cell 20. As a result, the powersupply switch cells 20 can be formed by the switches SW0 to SW3 havingthe minimum necessary size. This results in achievement of an effect toreduce leakage current, an effect to decrease the area of the powersupply switch cell 20, and an effect to shorten the design period.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alternations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalent thereof.

What is claimed is:
 1. A semiconductor integrated circuit, comprising: aplurality of circuit cells; a plurality of sub wiring lines disposed ina first direction and individually shared by predetermined ones of theplural circuit cells, a plurality of the predetermined ones of theplural circuit cells being juxtaposed in the first direction; aplurality of power supply switch cells for controlling connection anddisconnection between individual sub wiring lines and said main wiringline in response to a control signal inputted thereto; and an auxiliarywiring line for connecting the plural sub wiring lines to each other,the auxiliary wiring line extending in a second direction that isperpendicular to the first direction, wherein the predetermined ones ofthe plural circuit cells include a first circuit cell that is located ata left side of one of the sub wiring lines and a second circuit cellthat is located at a right side of said one of the sub wiring lines. 2.A semiconductor integrated circuit as set forth in claim 1, wherein saidone of the power supply switch cells and said second one of the powersupply switch cells are simultaneously controllable by a control signalon the control line.
 3. A semiconductor integrated circuit as set forthin claim 1, wherein said first direction differs from said seconddirection.
 4. A semiconductor integrated circuit as set forth in claim1, wherein said first direction is perpendicular to said seconddirection.
 5. A semiconductor integrated circuit as set forth in claim1, wherein said main line crosses said branch lines.
 6. A semiconductorintegrated circuit as set forth in claim 1, wherein said control linecrosses said branch lines.
 7. A semiconductor integrated circuit as setforth in claim 1, wherein a portion of the interconnect layer is betweensaid main line and said row of the power supply switch cells.
 8. Asemiconductor integrated circuit as set forth in claim 1, furthercomprising: a contact directly electrically connecting said main line toone of the branch lines, said one of the branch lines being directlyelectrically connected to said one of the power supply switch cells. 9.A semiconductor integrated circuit as set forth in claim 8, wherein saidcontact is between said main line and said one of the branch lines. 10.A semiconductor integrated circuit as set forth in claim 8, furthercomprising: an auxiliary line directly electrically connected to asecond one of the branch lines, said auxiliary line extending along saidfirst direction.
 11. A semiconductor integrated circuit as set forth inclaim 10, wherein said auxiliary line is in said upper layer.
 12. Asemiconductor integrated circuit as set forth in claim 10, wherein saidmain line is between said control line and said auxiliary line.
 13. Asemiconductor integrated circuit as set forth in claim 10, furthercomprising: a circuit cell directly electrically connected said one ofthe branch lines and another of the branch lines, said auxiliary wiringline being between said main line and said circuit cell.
 14. Asemiconductor integrated circuit as set forth in claim 13, wherein athreshold voltage for a transistor in one of the circuit cells is higherthan a threshold voltage for a transistor in said one of the powersupply switch cells.
 15. A semiconductor integrated circuit as set forthin claim 10, wherein said one of the power supply switch cells iscontrollable to provide electrical connection and disconnection betweensaid one of the branch lines and said second one of the branch lines.16. A semiconductor integrated circuit as set forth in claim 15, whereinsaid second one of the power supply switch cells is controllable toprovide electrical connection and disconnection between said one of thebranch lines and a third one of the branch lines.
 17. A semiconductorintegrated circuit as set forth in claim 1, further comprising: a thirdone of the power supply switch cells directly electrically connected tosaid control line, said third one of the power supply switch cells beingcontrollable to provide electrical connection and disconnection betweensaid main line and another of the branch lines.
 18. A semiconductorintegrated circuit as set forth in claim 17, wherein said one of thepower supply switch cells is between said second one of the power supplyswitch cells being and said third one of the power supply switch cells.19. A semiconductor integrated circuit as set forth in claim 1, furthercomprising: a different control line extending along said firstdirection, a different one of the power supply switch cells beingdirectly electrically connected to said different control line.
 20. Asemiconductor integrated circuit comprising: an interconnect layer ofthe semiconductor integrated circuit between a substrate region of thesemiconductor integrated circuit and an upper layer of the semiconductorintegrated circuit; a main line in said upper layer, said main lineextending along a first direction; branch lines in said interconnectlayer, said branch lines extending along a second direction; a row ofpower supply switch cells in said substrate region, said row of thepower supply switch cells extending along said first direction; acontrol line extending along said first direction, one of the powersupply switch cells and a second one of the power supply switch cellsbeing directly electrically connected to said control line.
 21. Asemiconductor integrated circuit, comprising: branch lines that extendin parallel along a first direction; a main line that extends along thefirst direction in parallel to the branch lines; an auxiliaryinterconnect that extends along a second direction so as to cross thebranch lines and the main line; a contact that electrically connects afirst one of the branch lines with the auxiliary interconnect; and afirst switch cell that is electrically connected to the main line andthe first one of the branch lines, wherein the first switch cell iscontrollable by a control signal to electrically disconnect the mainline from the first one of the branch lines.
 22. A semiconductorintegrated circuit as set forth in claim 21, wherein the first directiondiffers from the second direction.
 23. A semiconductor integratedcircuit as set forth in claim 21, wherein the first direction isperpendicular to the second direction.
 24. A semiconductor integratedcircuit as set forth in claim 21, wherein the first switch cell iscontrollable by the control signal to electrically connect the first oneof the branch lines with the main line.
 25. A semiconductor integratedcircuit as set forth in claim 21, further comprising: a first circuitcell that is electrically connected to the first one of the branchlines.
 26. A semiconductor integrated circuit as set forth in claim 25,wherein a threshold voltage for a transistor in the first switch cell ishigher than a threshold voltage for a transistor in the first circuitcell.
 27. A semiconductor integrated circuit as set forth in claim 25,further comprising: a second switch cell that is electrically connectedto the main line and a second one of the branch lines.
 28. Asemiconductor integrated circuit as set forth in claim 27, wherein themain line is between the first one of the branch lines and the secondone of the branch lines.
 29. A semiconductor integrated circuit as setforth in claim 27, wherein the second switch cell is controllable by thecontrol signal to electrically disconnect the main line from the secondone of the branch lines.
 30. A semiconductor integrated circuit as setforth in claim 27, wherein the second switch cell is controllable by thecontrol signal to electrically connect the second one of the branchlines with the main line.
 31. A semiconductor integrated circuit as setforth in claim 27, further comprising: a second circuit cell that iselectrically connected to the second one of the branch lines.
 32. Asemiconductor integrated circuit as set forth in claim 27, furthercomprising: another contact that electrically connects the second one ofthe branch lines with the auxiliary interconnect.
 33. A semiconductorintegrated circuit as set forth in claim 21, further comprising: acontrol line that crosses the branch lines.
 34. A semiconductorintegrated circuit as set forth in claim 33, wherein the control line isconfigured to supply the control signal to the first switch cell.
 35. Asemiconductor integrated circuit as set forth in claim 21, wherein theauxiliary interconnect is electrically connected to each of the branchlines.
 36. A semiconductor integrated circuit as set forth in claim 21,wherein the auxiliary interconnect is electrically connected directly toeach of the branch lines.